 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| a FEATURES Single-Supply Operation: 2.7 V to 12 V Wide Input Voltage Range Rail-to-Rail Output Swing Low Supply Current: 300 A/Amp Wide Bandwidth: 3 MHz Slew Rate: 0.5 V/s Low Offset Voltage: 700 V No Phase Reversal APPLICATIONS Industrial Process Control Battery Powered Instrumentation Power Supply Control and Protection Telecom Remote Sensors Low Voltage Strain Gage Amplifiers DAC Output Amplifier Micropower Single-Supply Rail-to-Rail Input/Output Op Amps OP191/OP291/OP491 OP191/OP291/OP491 PIN CONFIGURATIONS 8-Lead Narrow-Body SO (S Suffix) 1 2 3 4 8 8-Lead Epoxy DIP (P Suffix) NC -INA +INA -V 1 2 3 4 OP191 7 6 5 OP191 8 7 6 5 NC V+ OUTA NC NC = NO CONNECT 8-Lead Narrow-Body SO (S Suffix) 1 2 3 4 8 8-Lead Epoxy DIP (P Suffix) OUTA -INA +INA -V 1 2 3 4 OP291 7 6 5 OP291 8 7 6 5 +V OUTB -INB +INB GENERAL DESCRIPTION The OP191, OP291 and OP491 are single, dual and quad micropower, single-supply, 3 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. All are guaranteed to operate from a 3 volt single supply as well as 5 volt dual supplies. Fabricated on Analog Devices' CBCMOS process, the OP191 family has a unique input stage that allows the input voltage to safely extend 10 volts beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies. Applications for these amplifiers include portable telecom equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include Hall effect, piezo electric, and resistive transducers. The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and maintain high signal-to-noise ratios. The OP191/OP291/OP491 are specified over the extended industrial (-40C to +125C) temperature range. The OP191 single and OP291 dual amplifiers are available in 8-pin plastic DIPs and SO surface mount packages. The OP491 quad is available in 14-pin DIPs and narrow 14-pin SO packages. Consult factory for OP491 TSSOP availability. 14-Lead Epoxy DIP (P Suffix) OUTA 1 -INA 2 14 OUTD 13 -IND 12 +IND 14-Lead SO (S Suffix) OUTA 1 -INA 2 4 6 +INA 3 +V -INB 14 OUTD 13 -IND 12 +IND +INA 3 +V 4 OP491 11 -V 10 +INC 9 -INC 8 OUTC OP491 11 -V 10 +INC 9 8 -INC OUTC +INB 5 OUTB 7 +INB 5 -INB 6 OUTB 7 14-Lead TSSOP (RU Suffix) 1 2 3 4 5 6 7 14 13 12 OP491 11 10 9 8 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 OP191/OP291/OP491-SPECIFICATIONS ELECTRICAL SPECIFICATIONS (@ V = +3.0 V, V S CM = 0.1 V, VO = 1.4 V, TA = +25C unless otherwise noted) Min Typ 80 80 30 0.1 0 70 65 25 Max 500 1 700 1.25 50 70 8 16 3 Units V mV V mV nA nA nA nA V dB dB V/mV V/mV V/C pA/C pA/C V V V V mV mV mV mV mA mA dB dB A A V/s V/s kHz s MHz Degrees dB V p-p nV/Hz pA/Hz Parameter INPUT CHARACTERISTICS Offset Voltage OP191G OP291/OP491G Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS VOS IB IOS CMRR AVO VOS/T IB/T IOS/T VOH Conditions -40 TA +125C -40 TA +125C -40 TA +125C -40 TA +125C VCM = 0 V to 2.9 V -40 TA +125C RL = 10 k , VO = 0.3 V to 2.7 V -40 TA +125C 90 87 70 50 1.1 100 20 2.99 2.98 2.9 2.8 4.5 40 Output Voltage Low VOL Short Circuit Limit Open Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Specifications subject to change without notice. ISC ZOUT PSRR ISY RL = 100 k to GND -40C to +125C RL = 2 k to GND -40C to +125C RL = 100 k to V+ -40C to +125C RL = 2 k to V+ -40C to +125C Sink/Source -40C to +125C f = 1 MHz, AV = 1 VS = 2.7 V to 12 V -40C TA +125C VO = 0 V -40C TA +125C RL = 10 k RL = 10 k 1% Distortion To 0.01% 2.95 2.90 2.8 2.70 8.75 6.0 13.5 10.5 200 110 110 200 330 0.4 0.4 1.2 22 3 45 145 2 35 0.8 10 35 75 130 80 75 350 480 +SR -SR BWP tS GBP O CS en p-p en in f = 1 kHz, RL = 10 k 0.1 Hz to 10 Hz f = 1 kHz -2- REV. 0 OP191/OP291/OP491 ELECTRICAL SPECIFICATIONS (@ V = +5.0 V, V S CM = 0.1 V, VO = 1.4 V, TA = +25C unless otherwise noted) Min Typ 80 80 30 0.1 0 70 65 25 Max 500 1.0 700 1.25 50 60 8 16 5 Units V mV V mV nA nA nA nA V dB dB V/mV V/mV V/C pA/C pA/C V V V V mV mV mV mV mA mA dB dB A A V/s V/s kHz s MHz Degrees dB V p-p nV/Hz pA/Hz Parameter INPUT CHARACTERISTICS Offset Voltage OP191 OP291/OP491 Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS VOS IB IOS CMRR AVO VOS/T IB/T IOS/T VOH Conditions -40 TA +125C -40 TA +125C -40 TA +125C -40 TA +125C VCM = 0 V to 4.9 V -40 TA +125C RL = 10 k , VO = 0.3 V to 4.7 V -40 TA +125C -40 TA +125C 93 90 70 50 1.1 100 20 4.99 4.98 4.85 4.75 4.5 40 Output Voltage Low VOL Short Circuit Limit Open Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density ISC ZOUT PSRR ISY RL = 100 k to GND -40C to +125C RL = 2 k to GND -40C to +125C RL = 100 k to V+ -40C to +125C RL = 2 k to V+ -40C to +125C Sink/Source -40C to +125C f = 1 MHz, AV = 1 VS = 2.7 V to 12 V -40 TA +125C VO = 0 V -40 TA +125C RL = 10 k RL = 10 k 1% Distortion To 0.01% 4.95 4.90 4.8 4.65 8.75 6.0 13.5 10.5 200 110 110 220 350 0.4 0.4 1.2 22 3 45 145 2 35 0.8 10 35 75 155 80 75 400 500 +SR -SR BWP tS GBP O CS en p-p en in f = 1 kHz, RL = 10 k 0.1 Hz to 10 Hz f = 1 kHz NOTES +5 V specifications are guaranteed by +3 V and 5 V testing. Specifications subject to change without notice. REV. 0 -3- OP191/OP291/OP491 ELECTRICAL SPECIFICATIONS (@ V = 5.0 V, -4.9 V V O CM +4.9 V, TA = +25C unless otherwise noted) Min Typ 80 80 30 0.1 -5 75 67 25 Max 500 1 700 1.25 50 70 8 16 +5 Units V mV V mV nA nA nA nA V dB dB V/mV V/C pA/C pA/C V V V V mA mA dB dB A A V/s kHz s MHz Degrees dB V p-p nV/Hz pA/Hz Parameter INPUT CHARACTERISTICS Offset Voltage OP191 OP291/OP491 Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing Symbol VOS VOS IB IOS CMR AVO VOS/T IB/T IOS/T VO Conditions -40 TA +125C -40 TA +125C -40 TA +125C -40 TA +125C VCM = 5 V -40 TA +125C RL = 10 k, VO = 4.7 V, -40 TA +125C 100 97 70 50 1.1 100 20 4.99 4.98 4.95 4.75 16 13 200 110 100 260 390 0.5 1.2 22 3 45 145 2 35 0.8 Short Circuit Limit Open Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Specifications subject to change without notice. ISC ZOUT PSRR ISY RL = 100 k to GND -40C to +125C RL = 2 k to GND -40 TA +125C Sink/Source -40C to +125C f = 1 MHz, AV = 1 VS = 5 V -40 TA +125C VO = 0 V -40 TA +125C RL =10 k 1% Distortion To 0.01% 4.93 4.90 4.80 4.65 8.75 6 80 70 420 550 SR BWP tS GBP O CS en p-p en in f = 1 kHz 0.1 Hz to 10 Hz f = 1 kHz 5V 100 90 INPUT OUTPUT VS = 5V RL = 2k AV = +1 VIN = 20Vp-p 10 0% 5V 200s Figure 1. Input and Output with Inputs Overdriven by 5 V -4- REV. 0 OP191/OP291/OP491 WAFER TEST LIMITS (@ V = +3.0 V, V S CM = 0.1 V, TA = +25C unless otherwise noted) Conditions Limit 300 50 8 V- to V+ 70 80 50 2.8 75 350 Units V max nA max nA V min dB min dB min V/mV min V min mV max A max Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage High Output Voltage Low Supply Current/Amplifier Symbol VOS IB IOS VCM CMRR PSRR AVO VOH VOL ISY VCM = 0 V to +2.9 V V = 2.7 V to +12 V R L = 10 k R L = 2 k to GND R L = 2 k to V+ VO = 0 V, R L = NOTE Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .GND to VS + 10 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite Storage Temperature Range P, S, RU Packages . . . . . . . . . . . . . . . . . . . -65C to +150C Operating Temperature Range OP191/OP291/OP491G . . . . . . . . . . . . . . . -40C to +125C Junction Temperature Range P, S, RU Packages . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C Package Type 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 14-Pin Plastic DIP (P) 14-Pin SOIC (S) 14-Pin TSSOP (RU) JA2 103 158 76 120 180 JC 43 43 33 36 35 Units C/W C/W C/W C/W C/W Model OP191GP OP191GS OP191GBC OP291GP OP291GS OP291GBC OP491GP OP491GS OP491HRU OP491GBC Temperature Range -40C to +125C -40C to +125C +25C -40C to +125C -40C to +125C +25C -40C to +125C -40C to +125C -40C to +125C +25C Package Description 8-Pin Plastic DIP 8-Pin SOIC DICE 8-Pin Plastic DIP 8-Pin SOIC DICE 14-Pin Plastic DIP 14-Pin SOIC 14-Pin TSSOP DICE Package Option N-8 SO-8 N-8 SO-8 N-14 SO-14 RU-14 NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for the worst case conditions; i.e., JA is specified for device in socket for P-DIP packages; JA is specified for device soldered in circuit board for TSSOP and SOIC packages. 2 1 14 13 DICE CHARACTERISTICS 3 12 1 8 7 7 4 2 11 2 6 6 3 3 5 5 10 4 4 6 7 8 9 OP191 Die Size 0.047 x 0.066 Inch, 3,102 Sq. Mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 74. OP291 Die Size 0.070 x 0.070 Inch, 4,900 Sq. Mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 146 OP491 Die Size 0.070 x 0.110 Inch, 7,700 Sq. Mils. Substrate (Die Backside) Is Connected to V+. Transistor Count, 290. REV. 0 -5- OP191/OP291/OP491-Typical Performance Characteristics 180 VS = +3V 160 T = +25C A BASED ON 1200 140 OP AMPS 120 UNITS 100 80 60 40 20 120 100 0 INPUT OFFSET VOLTAGE - mV VS = +3V -40C < TA < +125C BASED ON 600 OP AMPS VS = +3V -0.02 -0.04 VCM = 0V -0.06 VCM = 3V -0.08 -0.1 VCM = 2.9V -0.12 -0.14 VCM = 0.1V 80 UNITS 60 40 20 0 -0.18 0 0.14 -0.10 -0.02 0.06 INPUT OFFSET VOLTAGE - mV 0.22 0 1 2 3 4 5 6 INPUT OFFSET VOLTAGE - V/ C 7 -40 85 25 TEMPERATURE - C 125 Figure 2. OP291 Input Offset Voltage Distribution, VS = +3 V Figure 3. OP291 Input Offset Voltage Drift Distribution, VS = +3 V 0 Figure 4. Input Offset Voltage vs. Temperature, VS = +3 V 40 30 36 30 VS = +3V VCM = 3V -0.2 INPUT OFFSET CURRENT - nA INPUT BIAS CURRENT - nA 10 0 -10 -20 -30 -40 -50 -60 -40 VS = +3V VCM = 2.9V -0.4 -0.6 INPUT BIAS CURRENT - nA 125 20 VS = +3V VCM = 0.1V VCM = 2.9V VCM = 3V 24 18 12 6 0 -6 -12 -18 -24 -30 -36 -0.8 VCM = 0V -1.0 -1.2 -1.4 -1.6 -1.8 -40 VCM = 0.1V VCM = 0V 25 85 TEMPERATURE - C 125 25 85 TEMPERATURE - C 0 0.30 0.60 0.90 1.2 1.5 1.8 2.1 2.4 2.7 3.0 INPUT COMMON MODE VOLTAGE - Volts Figure 5. Input Bias Current vs. Temperature, VS = +3 V Figure 6. Input Offset Current vs. Temperature, VS = +3 V Figure 7. Input Bias Current vs. Common-Mode Voltage, VS = +3 V 3.00 +VO @ RL = 100k 2.95 OUTPUT SWING - Volts OPEN-LOOP GAIN - dB 160 140 120 100 80 60 40 20 0 0 45 90 135 180 225 1k 10k 100k 1M FREQUENCY - Hz 270 10M VS = +3V TA = +25C 1200 RL = 100k, VCM = 2.9V RL = 100k, VCM = 0.1V 1000 OPEN-LOOP GAIN -V/mV PHASE SHIFT - Degrees 800 2.90 +VO @ RL = 2k 2.85 600 400 2.80 VS = +3V 2.75 -40 200 VS = 3V, VO = 0.3V / 2.7V 0 -40 25 85 TEMPERATURE - C 125 -20 -40 100 25 85 TEMPERATURE - C 125 Figure 8. Output Voltage Swing vs. Temperature, VS = +3 V Figure 9. Open-Loop Gain & Phase vs. Frequency, VS = +3 V Figure 10. Open-Loop Gain vs. Temperature, VS = +3 V -6- REV. 0 OP191/OP291/OP491 50 40 CLOSED-LOOP GAIN - dB 160 90 CMRR VS = +3V TA = +25C CMRR - dB VS = +3V TA = +25C 140 120 100 VS = +3V 89 30 20 10 0 -10 -20 -30 -40 -50 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M CMRR - dB 88 80 60 40 20 0 -20 -40 100 1k 10k 100k FREQUENCY - Hz 1M 10M 87 86 85 84 -40 25 85 TEMPERATURE - C 125 Figure 11. Closed-Loop Gain vs. Frequency, VS = +3 V 160 140 120 100 PSRR VS = +3V TA = +25C Figure 12. CMRR vs. Frequency, VS = +3 V 113 VS = +3V 112 Figure 13. CMRR vs. Temperature, VS = +3 V 1.6 1.4 1.2 VS = +3V +SR 111 SLEW RATE - V/s 1.0 0.8 0.6 0.4 PSRR - dB 80 60 40 20 0 -20 -40 100 1k 10k -PSRR +PSRR PSRR - dB 110 109 108 107 -40 0.2 0 -40 -SR 100k 1M 10M FREQUENCY - Hz 85 TEMPERATURE - C 25 125 85 25 TEMPERATURE - C 125 Figure 14. PSRR vs. Frequency, VS = +3 V 0.35 SUPPLY CURRENT/AMPLIFIER - mA Figure 15. PSRR vs. Temperature, VS = +3 V 2.8 MAXIMUM OUTPUT SWING - Volts Figure 16. Slew Rate vs. Temperature, VS = +3 V VS = +3V 0.30 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 VIN = +2.8Vp-p VS = +3V AV = +1 RL = 100k MKR: 36.2 nV/Hz 0.25 100 90 0.20 0.15 10 0% 0.10 0.05 -40 25 85 125 TEMPERATURE - C 1.0 0.1 0.5 1.0 10 30 50 70 100 150 200 250 300 FREQUENCY - kHz MKR: 0 Hz 1000 Hz BW: 2.5kHz 15.0 Hz Figure 17. Supply Current vs. Temperature, VS = +3 V, +5 V, 5 V Figure 18. Maximum Output Swing vs. Frequency, VS = +3 V Figure 19. Voltage Noise Density, VS = +3 V to 5 V, AVO = 1000 REV. 0 -7- OP191/OP291/OP491-Typical Performance Characteristics 70 60 50 UNITS VS = +5V TA = +25C BASED ON 600 OP AMPS 120 VS = +5V -40C < TA < +125C BASED ON 600 OP AMPS 0.15 VS = +5V 0.10 VCM = 0V VOS - mV 100 80 UNITS 40 30 20 10 0 -.50 0.05 60 0 VCM = +5V 40 20 -0.05 0 -.30 -.10 .10 .30 .50 INPUT OFFSET VOLTAGE - mV 0 1.0 2.0 3.0 4.0 5.0 6.0 INPUT OFFSET VOLTAGE - V/ C 7.0 -0.1 -40 85 25 TEMPERATURE - C 125 Figure 20. OP291 Input Offset Voltage Distribution, VS = +5 V 40 -IB Figure 21. OP291 Input Offset Voltage Drift Distribution, VS = +5 V 1.6 Figure 22. Input Offset Voltage vs. Temperature, VS = +5 V 36 INPUT OFFSET CURRENT - nA 30 20 10 VS = +5V VCM = 5V +IB VS = +5V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -40 VCM = 5V 25 85 TEMPERATURE - C 125 VCM = 0V 30 VS = +5V INPUT BIAS CURRENT - nA 24 18 12 6 0 -6 -12 -18 -24 -30 -36 0 5 1 2 3 4 COMMON MODE INPUT VOLTAGE - Volts I B - nA 0 -10 -20 -30 -40 -40 VCM = 0V -IB +IB 85 25 TEMPERATURE - C 125 Figure 23. Input Bias Current vs. Temperature, VS = +5 V Figure 24. Input Offset Current vs. Temperature, VS = +5 V Figure 25. Input Bias Current vs. Common-Mode Voltage, VS = +5 V 140 5.00 RL = 100k 4.95 160 140 VS = +5V TA = +25C VS = +5V 120 OPEN-LOOP GAIN - V/mV OUTPUT SWING - Volts OPEN-LOOP GAIN - dB 120 PHASE SHIFT - Degrees RL = 100k, VCM = 5V 100 80 60 RL = 100k, VCM = 0V 40 20 RL = 2k, VCM = 0V 0 -40 25 85 TEMPERATURE - C 125 RL = 2k, VCM = 5V 4.90 100 80 60 40 20 0 0 45 90 135 180 225 1k 10k 100k 1M 10M 270 4.85 RL = 2k 4.80 4.75 VS = +5V 4.70 -40 25 85 125 -20 -40 100 TEMPERATURE - C FREQUENCY - Hz Figure 26. Output Voltage Swing vs. Temperature, VS = +5 V Figure 27. Open-Loop Gain & Phase vs. Frequency, VS = +5 V Figure 28. Open-Loop Gain vs. Temperature, VS = +5 V -8- REV. 0 OP191/OP291/OP491 50 40 CLOSED-LOOP GAIN - dB 160 VS = +5V TA = +25C 96 CMRR VS = +5V TA = +25C 140 120 100 95 94 CMRR - dB 93 92 91 90 89 88 87 VS = +5V 30 20 10 0 -10 -20 -30 -40 -50 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M CMRR - dB 80 60 40 20 0 -20 -40 100 1k 10k 100k 1M FREQUENCY - Hz 10M 86 -40 85 25 TEMPERATURE - C 125 Figure 29. Closed-Loop Gain vs. Frequency, VS = +5 V 160 140 120 100 PSRR VS = +5V TA = +25C Figure 30. CMRR vs. Frequency, VS = +5 V 0.6 Figure 31. CMRR vs. Temperature, VS = +5 V 0.50 0.45 VS = +5V 0.5 0.40 +SR 0.35 -SR 0.30 0.25 0.20 PSRR - dB SR - V/s 80 60 40 20 -PSRR +PSRR +SR 0.3 -SR 0.2 SR - V/s VS = +5V 125 0.4 0.15 0.10 0.05 0 -40 25 85 TEMPERATURE - C 125 P 0 -20 -40 100 1k 10k 100k 1M FREQUENCY - Hz 10M 0.1 0 -40 85 TEMPERATURE - C 25 Figure 32. PSRR vs. Frequency, VS = +5 V 20 Figure 33. OP291 Slew Rate vs. Temperature, VS = +5 V 80 Figure 34. OP491 Slew Rate vs. Temperature, VS = +5 V 5.0 VIN = +4.8Vp-p VS = +5V AV = +1 RL = 100k 4 PARTS VS = 5V SHORT CIRCUIT CURRENT - mA 18 16 14 12 10 8 6 4 -40 +ISC, VS = +3V +ISC, VS = 5V -ISC, VS = 5V 70 60 VOLTAGE - V MAXIMUM OUTPUT SWING - Volts 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 50 40 30 20 A 10k B 10k VIN = 10Vp-p @ 1kHz 1k VO -ISC, VS = +3V 10 0 85 25 TEMPERATURE - C 125 0 500 1000 1500 2000 FREQUENCY - Hz 2500 0 0.1 0.5 1.0 10 30 50 70 100 150 200 250 300 FREQUENCY - kHz Figure 35. Short Circuit Current vs. Temperature, VS = +3 V, +5 V, 5 V Figure 36. Channel Separation, VS = 5 V Figure 37. Maximum Output Swing vs. Frequency, VS = +5 V REV. 0 -9- OP191/OP291/OP491-Typical Performance Characteristics 10 MAXIMUM OUTPUT SWING - Volts 9 8 7 6 5 4 3 2 1 INPUT OFFSET VOLTAGE - mV VIN = +9.8Vp-p VS = 5V AV = +1 RL = 100k 4 PARTS 0.15 VS = 5V 50 40 VS = 5V +IB VCM = +5V -IB 0.10 VCM = -5V 0.05 IB - nA 30 20 10 0 -10 0 VCM = +5V -20 -30 -40 VCM = -5V -IB +IB -0.05 0 0.1 0.5 1.0 10 30 50 70 100 150 200 250 300 FREQUENCY - kHz -0.1 -40 25 85 TEMPERATURE - C 125 -50 -40 25 85 TEMPERATURE - C 125 Figure 38. Maximum Output Swing vs. Frequency, VS = 5 V 1.6 VS = 5V Figure 39. Input Offset Voltage vs. Temperature, VS = 5 V 36 Figure 40. Input Bias Current vs. Temperature, VS = 5 V 5.00 INPUT OFFSET CURRENT - nA 1.4 INPUT BIAS CURRENT - nA 24 OUTPUT VOLTAGE SWING - Volts VS = 5V 4.95 4.90 4.85 4.80 4.75 0 -4.75 -4.80 -4.85 -4.90 -4.95 VS = 5V RL = 100k 1.2 1.0 0.8 0.6 0.4 0.2 0 VCM = -5V 12 RL = 2k 0 -12 -24 RL = 2k RL = 100k 25 85 TEMPERATURE - C 125 VCM = +5V -0.2 -40 -36 85 25 TEMPERATURE - C 125 -5 -4 -3 -2 -1 0 1 23 4 5 COMMON MODE INPUT VOLTAGE - Volts -5.00 -40 Figure 41. Input Offset Current vs. Temperature, VS = 5 V Figure 42. Input Bias Current vs. Common-Mode Voltage, VS = 5 V Figure 43. Output Voltage Swing vs. Temperature, VS = 5 V 70 60 50 VS = 5V TA = +25C 0 45 90 135 180 225 270 1k 10k 100k FREQUENCY - Hz 1M 10M 200 180 VS = 5V CLOSED-LOOP GAIN - dB 50 40 30 20 10 0 -10 -20 -30 -40 -50 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M VS = 5V TA = +25C OPEN-LOOP GAIN - V/mV 160 140 120 100 80 65 40 25 0 -40 25 85 TEMPERATURE - C 125 RL = 2k RL = 100k OPEN-LOOP GAIN - dB 30 20 10 0 -10 -20 -30 PHASE SHIFT - Degrees 40 Figure 44. Open-Loop Gain & Phase vs. Frequency, VS = 5 V Figure 45. Open-Loop Gain vs. Temperature, VS = 5 V Figure 46. Closed-Loop Gain vs. Frequency, VS = 5 V -10- REV. 0 OP191/OP291/OP491 160 140 120 100 CMRR VS = 5V TA = +25C 102 101 100 VS = 5V 160 140 120 100 PSRR VS = 5V TA = +25C CMRR - dB CMRR - dB 99 98 97 96 95 94 93 80 60 40 20 0 -20 -40 100 1k 10k 100k FREQUENCY - Hz 1M 10M PSRR - dB 80 60 40 20 0 -20 -PSRR +PSRR 92 -40 25 85 TEMPERATURE - C 125 -40 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 47. CMRR vs. Frequency, VS = 5 V 115 VS = 5V OP491 110 OP291 Figure 48. CMRR vs. Temperature, VS = 5 V 0.7 0.6 Figure 49. PSRR vs. Frequency, VS = 5 V 1k VS = 5V 900 800 VS = +3V TA = +25C 0.5 SR - V/s +SR 700 PSRR - dB 0.4 0.3 0.2 ZOUT - 105 -SR 600 500 400 300 200 AVCL = 100 AVCL = 10 100 1k AVCL = +1 10M 100 95 0.1 90 -40 100 0 0 25 85 TEMPERATURE - C 125 -40 25 85 TEMPERATURE - C 125 10k 100k 1M FREQUENCY - Hz Figure 50. OP291/OP491 PSRR vs. Temperature, VS = 5 V Figure 51. Slew Rate vs. Temperature, VS = 5 V Figure 52. Output Impedance vs. Frequency 1.00V 100 90 2.00V 100 90 INPUT INPUT VS = +3V RL = 200k 10 OUTPUT 10 0% VS = 5V RL = 200k AV = +1V/V 1.00V 2.00s 100mV 500mV 2.00s 100mV OUTPUT 0% Figure 53. Large Signal Transient Response, VS = +3 V Figure 54. Large Signal Transient Response, VS = 5 V REV. 0 -11- OP191/OP291/OP491 FUNCTIONAL DESCRIPTION The OP191/OP291/OP491 are single supply, micropower amplifiers featuring rail-to-rail inputs and outputs. In order to achieve wide input and output ranges, these amplifiers employ unique input and output stages. As the simplified schematic shows (Figure 55), the input stage is actually comprised of two differential pairs, a PNP pair and an NPN pair. These two stages do not actually work in parallel. Instead, only one or the other stage is on for any given input signal level. The PNP stage (transistors Q1 and Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. On the other hand, the NPN stage (transistors Q5 and Q6) is needed for input voltages up to and including the positive rail. For the majority of the input common-mode range, the PNP stage is active, as is evidenced by examining the graph of Input Bias Current vs. Common-Mode Voltage. Notice that the bias current switches direction at approximately 1.2 volts to 1.3 volts below the positive rail. At voltages below this, the bias current flows out of the OP291, indicating a PNP input stage. Above this voltage, however, the bias current enters the device, revealing the NPN stage. The actual mechanism within the amplifier for switching between the input stages is comprised of the transistors Q3, Q4, and Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually the emitters of Q1 and Q2 are high enough to turn Q3 on. This diverts the 8 A of tail current away from the PNP input stage, turning it off. Instead, the current is mirrored through Q4 and Q7 to activate the NPN input stage. Notice that the input stage includes 5 k series resistors and differential diodes, a common practice in bipolar amplifiers to protect the input transistors from large differential voltages. These diodes will turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current will flow between the input pins, limited only by the two 5 k resistors. Being aware of this characteristic is important in circuits where the amplifier may be operated open-loop, such as a comparator. Evaluate each circuit carefully to make sure that the increase in current does not affect the performance. The output stage of the OP191 family uses a PNP and an NPN transistor as do most output stages; however, the output transistors, Q32 and Q33, are actually connected with their collectors to the output pin to achieve the rail-to-rail output swing. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage does have inherent gain arising from the collectors and any external load impedance. Because of this, the open-loop gain of the amplifier is dependent on the load resistance. Input Overvoltage Protection As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, attention needs to be paid to the input overvoltage characteristic. When an overvoltage occurs, the amplifier could be damaged depending on the voltage level and the magnitude of the fault current. Figure 56 shows the characteristic for the OP191 family. This graph was generated with the power supplies at ground and a curve tracer connected to the input. As can be seen, when the input voltage exceeds either supply by more than 0.6 V, internal pn-junctions energize allowing current to flow from the input to the supplies. As described above, the OP291/OP491 does have 5 k resistors in series with each input, which helps limit the current. Calculating the slope of the current versus voltage in the graph confirms the 5 k resistor. 8A -IN Q22 Q26 Q32 Q23 5k +IN Q1 Q2 Q3 5k Q5 Q6 Q8 Q10 Q12 Q14 Q21 Q9 Q11 Q13 Q15 Q24 Q16 Q17 Q20 Q27 Q30 10pF Q31 Q28 VOUT Q18 Q4 Q7 Q19 Q25 Q29 Q33 Figure 55. Simplified Schematic -12- REV. 0 OP191/OP291/OP491 IIN 2mA 1mA -10V -5V 5V 10V VIN determines the lower limit of their common-mode range. With these devices, external clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excursions from exceeding the device's negative supply (i.e., GND), preventing a condition which could cause the output voltage to change phase. JFET-input amplifiers may also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it. The OP191 family is free from reasonable input voltage range restrictions due to its novel input structure. In fact, the input signal can exceed the supply voltage by a significant amount without causing damage to the device. As illustrated in Figure 57, the OP191 family can safely handle a 20 V p-p input signal on 5 V supplies without exhibiting any sign of output voltage phase reversal or other anomalous behavior. Thus no external clamping diodes are required. Overdrive Recovery -1mA -2mA Figure 56. Input Overvoltage Characteristics This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. In the case shown, for an input of 10 V over the supply, the current is limited to 1.8 mA. If the voltage is large enough to cause more than 5 mA of current to flow, then an external series resistor should be added. The size of this resistor is calculated by dividing the maximum overvoltage by 5 mA and subtracting the internal 5 k resistor. For example, if the input voltage could reach 100 V, the external resistor should be (100 V/5 mA) -5 k = 15 k. This resistance should be placed in series with either or both inputs if they are subjected to the overvoltages. For more information on general overvoltage characteristics of amplifiers refer to the 1993 System Applications Guide, available from the Analog Devices Literature Center. Output Voltage Phase Reversal The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large transient event, such as a comparator. The circuit shown in Figure 58 was used to evaluate the OP191 family's overload recovery time. The OP191 family takes approximately 8 s to recover from positive saturation and approximately 6.5 s to recover from negative saturation. R1 9k VIN 10V STEP 3 1/2 2 OP291 R2 10k 1 R3 10k VOUT Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range. Typically for single-supply bipolar op amps, the negative supply VS = 5V Figure 58. Overdrive Recovery Time Test Circuit 5s +5V VIN - 2.5V/DIV 100 90 100 90 5s 1/2 2 OP291 4 -5V 1 VOUT 10 0% VOUT - 2V/DIV 10 0% VIN 20Vp-p 3 8 20mV TIME - 200s/DIV TIME - 200s/DIV 20mV Figure 57. Output Voltage Phase Reversal Behavior REV. 0 -13- OP191/OP291/OP491 APPLICATIONS Single +3 V Supply, Instrumentation Amplifier Single Supply RTD Amplifier The OP291's low supply current and low voltage operation make it ideal for battery powered applications such as the instrumentation amplifier shown in Figure 59. The circuit utilizes the classic two op amp instrumentation amplifier topology, with four resistors to set the gain. The equation is simply that of a noninverting amplifier as shown in the figure. The two resistors labeled R1 should be closely matched to each other as well as both resistors labeled R2 to ensure good common-mode rejection performance. Resistor networks ensure the closest matching as well as matched drifts for good temperature stability. Capacitor C1 is included to limit the bandwidth and, therefore, the noise in sensitive applications. The value of this capacitor should be adjusted depending on the desired closed-loop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2 x R1C1). If AC-CMRR is critical, than a matched capacitor to C1 should be included across the second resistor labeled R1. +3V 5 VIN 3 1/2 2 OP291 R1 R2 1 8 1/2 OP291 6 4 The circuit in Figure 60 uses three op amps of the OP491 to develop a bridge configuration for an RTD amplifier that operates from a single +5 V supply. The circuit takes advantage of the OP491's wide output swing range to generate a high bridge excitation voltage of 3.9 V. In fact, because of the railto-rail output swing, this circuit will work with supplies as low as 4.0 V. Amplifier A1 servos the bridge to create a constant excitation current in conjunction with the AD589, a 1.235 V precision reference. The op amp maintains the reference voltage across the parallel combination of the 6.19 k and 2.55 M resistor, which generates a 200 A current source. This current splits evenly and flows through both halves of the bridge. Thus, 100 A flows through the RTD to generate an output voltage based on its resistance. A 3-wire RTD is used to balance the line resistance in both 100 legs of the bridge to improve accuracy. 200 10-TURNS GAIN = 274 +5V 7 26.7k 26.7k VOUT 100 RTD 2.55M 100 A3 A2 1/4 OP491 365 6.19k 365 100k 1/4 OP491 VOUT R2 R1 C1 A1 1/4 OP491 100k 0.01pF NOTE: ALL RESISTORS 1% OR BETTER R1 VOUT = (1 + --- ) V IN R2 100pF AD589 37.4k Figure 59. Single +3 V Supply Instrumentation Amplifier Because the OP291 accepts rail-to-rail inputs, the input common-mode range includes both ground and the positive supply of 3 V. Furthermore, the rail-to-rail output range ensures the widest signal range possible and maximizes the dynamic range of the system. Also, with its low supply current of 300 A/device, this circuit consumes a quiescent current of only 600 A, yet still exhibits a gain bandwidth of 3 MHz. A question may arise about other instrumentation amplifier topologies for single supply applications. For example, a variation on this topology adds a fifth resistor between the two inverting inputs of the op amps for gain setting. While that topology works well in dual supply applications, it is inherently not appropriate for single supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the circuits simply will not work in single supply situations unless a false ground between the supplies is created. +5V Figure 60. Single Supply RTD Amplifier Amplifiers A2 and A3 are configured in the two op amp IA discussed above. Their resistors are chosen to produce a gain of 274, such that each 1C increase in temperature results in a 10 mV change in the output voltage, for ease of measurement. A 0.01 F capacitor is included in parallel with the 100 k resistor on amplifier A3 to filter out any unwanted noise from this high gain circuit. This particular RC combination creates a pole at 1.6 kHz. -14- REV. 0 OP191/OP291/OP491 A +2.5 V Reference from a +3 V Supply In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic 2.5 V references require at least a minimum operating supply voltage of 4 V. The problem is exacerbated when the minimum operating system supply voltage is + 3 V. The circuit illustrated in Figure 61 is an example of a +2.5 V that operates from a single +3 V supply. The circuit takes advantage of the OP291's rail-to-rail input and output voltage ranges to amplify an AD589's 1.235 V output to +2.5 V. The OP291's low TCVOS of 1 V/C helps to maintain an output voltage temperature coefficient of less than 200 ppm/C. The circuit's overall temperature coefficient is dominated by R2 and R3's temperature coefficient. Lower tempco resistors are recommended. The entire circuit draws less than 420 A from a +3 V supply at +25C. The OP291 serves two functions. First, it is required to buffer the high output impedance of the DAC's VREF pin, which is on the order of 10 k. The op amp provides a low impedance output to drive any following circuitry. Secondly, the op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 to generate a 5.0 V output when the DAC is at full scale. If other output voltage ranges are needed, such as 0 to 4.095, the gain can easily be adjusted by altering the value of the resistors. A High Side Current Monitor R1 17.4k +3V 3 8 1/2 2 OP291 4 1 AD589 +2.5V REF RESISTORS = 1%, 100ppm/C POTENTIOMETER = 10 TURN, 100ppm/C R3 100k R2 100k P1 5k In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor's long-term reliability over a wide range of load current conditions. As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit illustrated in Figure 63 is an example of a +5 V, single-supply high side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP291's rail-to-rail input voltage range to sense the voltage drop across a 0.1 current shunt. A p-channel MOSFET used as the feedback element in the circuit converts the op amp's differential input voltage into a current. This current is then applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by: R Monitor Output = R2 x SENSE x I L R1 Figure 61. A +2.5 V Reference that Operates on a Single +3 V Supply +5 V Only, 12-Bit DAC Swings Rail-to-Rail The OP191 family is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range. Figure 62 shows the DAC8043 used in conjunction with the AD589 to generate a voltage output from 0 V to 1.23 V The DAC is actually operated in "voltage switching" mode where the reference is connected to the current output, IOUT, and the output voltage is taken from the VREF pin. This topology is inherently noninverting as opposed to the classic current output mode, which is inverting and, therefore, unsuitable for single supply. +5V 8 R1 17.8k 1.23V 3 IOUT VDD R FB 2 1 +5V GND CLK SR1 LD AD589 4 7 6 5 3 8 1/2 2 OP291 4 R4 100k 1% 1 D VOUT = ---- (5V) 4096 For the element values shown, the Monitor Output's transfer characteristic is 2.5 V/A. RSENSE 0.1 +5V +5V R1 100 3 8 1/2 OP291 2 4 G D R2 2.49k IL +5V 1 S M1 3N163 MONITOR OUTPUT DAC-8043 V REF Figure 63. A High-Side Load Current Monitor DIGITAL CONTROL R3 232 1% R2 32.4k 1% Figure 62. +5 V Only, 12-Bit DAC Swings Rail-to-Rail REV. 0 -15- OP191/OP291/OP491 A +3 V, Cold Junction Compensated Thermocouple Amplifier 390pF 37.4k The OP291's low supply operation makes it ideal for +3 V battery powered applications such as the thermocouple amplifier shown in Figure 64. The K-type thermocouple terminates in an isothermal block where the junctions' ambient temperature is continuously monitored using a simple 1N914 diode. The diode corrects the thermal EMF generated in the junctions by feeding a small voltage, scaled by the 1.5 M and 475 resistors, to the op amp. To calibrate this circuit, immerse the thermocouple measuring junction in a 0C ice bath, and adjust the 500 pot to zero volts out. Next, immerse the thermocouple in a 250C temperature bath or oven and adjust the Scale Adjust pot for an output voltage of 2.50 V. Within this temperature range, the K-type thermocouple is accurate to within 3C without linearization. 1.235V AD589 ISOTHERMAL BLOCK 1N914 10k 3.0V SCALE ADJUST 1.33M 20k 0.1F RXA 14 A1 13 1/4 OP491 12 20k, 1% 0.0047F 3.3k 10 9 1/4 OP491 20k, 1% A2 8 475, 1% 37.4k, 1% 0.1F TXA 20k 1% 20k 1% 6 1/4 5 OP491 0.033F 20k, 1% 750pF T1 1:1 A3 7 5.1V TO 6.2V ZENER 5 +3V OR +5V 7.15k 1% 1.5M 1% 24.9k 1% 24.3k 1% 4.99k 1% 2 500 10-TURN 3 ZERO ADJUST 2.1k 1% ALUMEL AL 4 2 8 VOUT 1 COLD JUNCTIONS CR CHROMEL K-TYPE THERMOCOUPLE 40.7V/C 11.2mV 475 1% OP291 4 1 0V = 0C 3V = 300C 1/4 OP491 3 A4 11 100k 100k 10F 0.1F Figure 64. A 3 V, Cold Junction Compensated Thermocouple Amplifier Single Supply, Direct Access Arrangement for Modems Figure 65. Single Supply Direct Access Arrangement for Modems An important building block in modems is the telephone line interface. In the circuit shown in Figure 65, a direct access arrangement is utilized for transmitting and receiving data from the telephone line. Amplifier A1 is the receiving amplifier, and amplifiers A2 and A3 are the transmitters. The forth amplifier, A4, generates a pseudo ground half way between the supply voltage and ground. This pseudo ground is needed for the ac coupled bipolar input signals. The transmit signal, TXA, is inverted by A2 and then reinverted by A3 to provide a differential drive to the transformer, where each amplifier supplies half the drive signal. This is needed because of the smaller swings associated with a single supply as opposed to a dual supply. Amplifier A1 provides some gain for the received signal, and it also removes the transmit signal present at the transformer from the receive signal. To do this, the drive signal from A2 is also fed to the noninverting input of A1 to cancel the transmit signal from the transformer. The OP491's bandwidth of 3 MHz and rail-to-rail output swings ensures that it can provide the largest possible drive to the transformer at the frequency of transmission. -16- REV. 0 OP191/OP291/OP491 A +3 V, 50 Hz/60 Hz Active Notch Filter with False Ground Single-Supply Half-Wave and Full-Wave Rectifiers To process ac signals in a single-supply system, it is often best to use a false-ground biasing scheme. A circuit that uses this approach is illustrated in Figure 66. In this circuit, a falseground circuit biases an active notch filter used to reject 50 Hz/ 60 Hz power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject power line frequency interference which often obscures low frequency physiological signals, such as heart rates, blood pressure readings, EEGs, EKGs, etcetera. This notch filter effectively squelches 60 Hz pickup at a filter Q of 0.75. Substituting 3.16 k resistors for the 2.67 k resistors in the twin-T section (R1 through R5) configures the active filter to reject 50 Hz interference. R2 2.67k R1 2.67k C1 1F 1 R3 2.67k C2 1F 5 R4 2.67k R5 1.33k (2.67k/2) 6 1/4 OP491 7 VOUT +3V 2 VIN 3 11 1/4 OP491 4 An OP191 family configured as a voltage follower operating on a single supply can be used as a simple half-wave rectifier in low-frequency (<2 kHz) applications. A full-wave rectifier can be configured with a pair of OP291s as illustrated in Figure 67. The circuit works in the following way: When the input signal is above 0 V, the output of amplifier A1 follows the input signal. Since the noninverting input of amplifier A2 is connected to A1's output, op amp loop control forces the A2's inverting input to the same potential. The result is that both terminals of R1 are equipotential; i.e., no current flows. Since there is no current flow in R1, the same condition exists upon R2; thus, the output of the circuit tracks the input signal. When the input signal is below 0 V, the output voltage of A1 is forced to 0 V. This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is at 0 V as well. The output voltage at VOUTA is then a full-wave rectified version of the input signal. If needed, a buffered, half-wave rectified version of the input signal is available at VOUTB. R1 100k +5V VIN 2Vpp <2kHz 3 2 8 1/2 OP291 1 6 1/2 5 OP291 7 R2 100k A1 A2 R6 100k C3 2F (1Fx2) R7 1k VOUT A FULL-WAVE RECTIFIED OUTPUT VOUT B R8 1k A2 4 A1 R11 100k +3V 9 10 C4 1F R10 1M C5 0.01F 1/4 OP491 8 R12 499 C6 1.5V 1F VOUT B (0.5V/DIV) VIN (1V/DIV) 100 90 HALF-WAVE RECTIFIED OUTPUT R9 1M 1V 500mV A3 10 Figure 66. A +3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter with False Ground VOUT A (0.5V/DIV) 0% 500mV TIME - 200s/DIV 200s Amplifier A3 is the heart of the false-ground bias circuit. It simply buffers the voltage developed by R9 and R10 and is the reference for the active notch filter. Since the OP491 exhibits a rail-to-rail input common-mode range, R9 and R10 are chosen to split the +3 V supply symmetrically. An in-the-loop compensation scheme is used around the OP491 that allows the op amp to drive C6, a 1 F capacitor, without oscillation. C6 maintains a low impedance ac ground over the operating frequency range of the filter. The filter section uses a pair of OP491s in a twin-T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-T section. Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the filter's passband symmetry. Using 1% resistors and 5% capacitors produces satisfactory results. Figure 67. Single-Supply Half-Wave and Full-Wave Rectifiers Using an OP291 REV. 0 -17- OP191/OP291/OP491 * OP491 SPICE Macro-model Rev. A, 5/94 * ARG/ADI * * Copyright 1994 by Analog Devices * * Refer to "README.DOC" file for License Statement. Use of * this model indicates your acceptance of the terms and pro* visions in the License Statement. * * Node assignments * noninverting input * inverting input * positive supply * negative supply * output * .SUBCKT OP491 1 2 99 50 45 * * INPUT STAGE * I1 99 7 8.06E-6 Q1 6 4 7 QP Q2 5 3 7 QP D1 3 99 DX D2 4 99 DX D3 3 4 DX D4 4 3 DX R1 3 8 5E3 R2 4 2 5E3 R3 5 50 6.4654E3 R4 6 50 6.4654E3 EOS 8 1 POLY(1) (16,39) -0.08E-3 1 IOS 3 4 50E-12 GB1 3 98 (21,98) 50E-9 GB2 4 98 (21,98) 50E-9 CIN 1 2 1E-12 * * 1ST GAIN STAGE * EREF 98 0 (39,0) 1 G1 98 9 (6,5) 31.667E-6 R7 9 98 1E6 EC1 99 10 POLY(1) (99,39) -0.52 1 EC2 11 50 POLY(1) (39,50) -0.52 1 D5 9 10 DX D6 11 9 DX * * 2ND GAIN STAGE AND DOMINANT POLE AT 1.25 Hz * G2 98 12 (9,39) 8E-6 R8 12 98 276.311E6 C2 12 98 16E-12 D7 12 13 DX D8 14 12 DX V1 99 13 0.58 V2 14 50 0.58 * * COMMON-MODE STAGE * ECM 15 98 POLY(2) (1,39) (2,39) 0 0.5 0.5 R9 15 16 1E6 R10 16 98 10 * * POLE AT 2.5 MHz * G3 98 18 (12,39) 1E-6 R11 18 98 1E6 C4 18 98 63.662E-15 * * BIAS CURRENT-VS-COMMON-MODE VOLTAGE * EP 97 0 (99,0) 1 VB 99 17 1.3 RB 17 50 1E9 E3 19 0 (15,17) 16 D13 19 20 DX R12 20 0 1E6 G4 98 21 (20,0) 1E-3 R13 21 98 5E3 D14 21 22 DY E4 97 22 (POLY(1) (99,98) -0.765 1 * * POLE AT 100 MHz * G6 98 40 (18,39) 1E-6 R20 40 98 1E6 C10 40 98 1.592E-15 * * OUTPUT STAGE * RS1 99 39 109.375E3 RS2 39 50 109.375E3 RO1 99 45 41.667 RO2 45 50 41.667 G7 45 99 (99,40) 24E-3 G8 50 45 (40,50) 24E-3 G9 98 60 (45,40) 24E-3 D9 60 61 DX D10 62 60 DX V7 61 98 DC 0 V8 98 62 DC 0 FSY 99 50 POLY(2) V7 V8 0.207E-3 1 1 D11 41 45 DZ D12 45 42 DZ V5 40 41 0.131 V6 42 40 0.131 .MODEL DX D() .MODEL DY D(IS=1E-9) .MODEL DZ D(IS=1E-6) .MODEL QP PNP(BF=66.667) .ENDS -18- REV. 0 OP191/OP291/OP491 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Epoxy DIP (P Suffix) 8-Lead Narrow-Body SO (S Suffix) 8 PIN 1 1 5 0.280 (7.11) 0.240 (6.10) 4 PIN 1 0.430 (10.92) 0.348 (8.84) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.195 (4.95) 0.115 (2.93) 0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 0.0688 (1.75) 0.0532 (1.35) 8 0 0.0500 (1.27) 0.0160 (0.41) 0.0196 (0.50) x 45 0.0099 (0.25) 1 4 8 5 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 14-Lead Epoxy DIP (P Suffix) 14 PIN 1 1 0.795 (20.19) 0.725 (18.42) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 7 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 8 0.280 (7.11) 0.240 (6.10) PIN 1 1 14-Lead Narrow-Body SO (S Suffix) 14 8 0.1574 (4.00) 0.1497 (3.80) 7 0.2440 (6.20) 0.2284 (5.80) 0.3444 (8.75) 0.3367 (8.55) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45 0.0099 (0.25) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.0098 (0.25) 0.0040 (0.10) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 8 0 0.0500 (1.27) 0.0160 (0.41) 14-Lead TSSOP (RU Suffix) 14 8 0.173 (4.40) 0.251 (6.40) COPLANARITY 0.003 (0.076) MAX PIN 1 1 7 0.1968 (5.00) 0.043 (1.10) 0.0040 (0.10) 0.026 (0.65) 0.005 (0.13) REV. 0 -19- -20- C1970-10-10/94 PRINTED IN U.S.A. |
Price & Availability of OP291GBC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |